////////////////////////////////////////////////////////////////////////////////
/// @file     adc.c
/// @author   AE TEAM
/// @brief    THIS FILE PROVIDES ALL THE SYSTEM FUNCTIONS.
////////////////////////////////////////////////////////////////////////////////
/// @attention
///
/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
///
/// <H2><CENTER>&COPY; COPYRIGHT MINDMOTION </CENTER></H2>
////////////////////////////////////////////////////////////////////////////////

// Define to prevent recursive inclusion
#define _ADC_C_

// Files includes
#include "adc.h"

////////////////////////////////////////////////////////////////////////////////
/// @addtogroup MM32_Example_Layer
/// @{

////////////////////////////////////////////////////////////////////////////////
/// @addtogroup ADC
/// @{

////////////////////////////////////////////////////////////////////////////////
/// @addtogroup ADC_Exported_Constants
/// @{

/////////////////////////////////////////////////////////////////////////////////
/// @brief   configure ADC1single transform  mode
/// @param   None
/// @retval  None
/////////////////////////////////////////////////////////////////////////////////
void ADC1_SingleChannel(void)
{
    RCC->AHBENR |= RCC_AHBENR_GPIOA; //enable GPIOA clock
    RCC->APB1ENR |= RCC_APB1ENR_ADC1; //enableADC1clock
    GPIOA->CRL &= ~(GPIO_CNF_MODE_MASK << GPIO_CRL_CNF_MODE_2_Pos); //IO status set
    GPIOA->CRL |= GPIO_CNF_MODE_AIN << GPIO_CRL_CNF_MODE_2_Pos; //IO status set    PA2

    RCC->APB1RSTR |= RCC_APB1RSTR_ADC1; //ADC1reset
    RCC->APB1RSTR &= ~(RCC_APB1RSTR_ADC1); //reset   end

    //ADC configure single soft trigger  transform mode
    ADC1->ADCFG &= ~(ADC_CFGR_PRE | ADC_CFGR_RSLTCTL);
    ADC1->ADCFG |= ADC_CFGR_PRE_16;
    ADC1->ADCR &= ~(ADC_CR_ALIGN | ADC_CR_MODE | ADC_CR_TRGSEL);
    ADC1->ADCR |= ADC_CR_CONTINUE;
    ADC1->CHANY0 &= ~ADC1_CHANY0_SEL0;
    ADC1->ANYCFG &= ~(ADC1_CHANY_CR_MDEN);
    ADC1->CHANY0 |= 5;     //chennl5
    ADC1->ANYCR |= ADC1_CHANY_CR_MDEN;

    ADC1->ADCFG |= ADCFG_ADEN;//ADC1enable
    ADC1->ADCR |= ADCR_ADST;//Start Conversion
}
/////////////////////////////////////////////////////////////////////////////////
/// @brief    getADC1 transform data
/// @param    None
/// @retval   None
/////////////////////////////////////////////////////////////////////////////////
u16 ADC1_SingleChannel_Get(void)
{
    u16 puiADData;
    //ADCR deviceADSTbit enable, soft start  transform
    ADC1->ADCR |= ADC_CR_CONTINUE;
    while(((ADC1->ADSTA ) & ADC_SR_ADIF) == 0);
    ADC1->ADSTA |= ADC_SR_ADIF;
    puiADData = ADC1->ADDATA & 0xfff;
    return puiADData;
}
/// @}


/// @}

/// @}
